1. Field of the Invention
The present invention relates to a semiconductor memory device having a replica circuit for controlling the sense timing of a sense amplifier.
2. Description of the Related Art
Along with an increase in the degree of integration of a large-scale integrated circuit (LSI), the occupation ratio of a static random access memory (SRAM) macro mounted on a system-on-chip (SoC) with respect to the chip area is increasingly becoming higher, and demand for a bulk SRAM megabit-order generator has arisen. In the bulk SRAM macro, it is difficult to generate a sense amplifier activation timing to ensure an optimum sense margin for each of the SRAM macros which are generated by a generator and have different capacities and configurations.
An example of a conventional semiconductor memory device having a replica circuit will be described.
In the replica circuit, a dummy word line connected to a dummy row decoder runs through dummy cells arrayed in the row direction and turns back. The dummy word line is then connected to dummy cells arrayed in the column direction through a dummy bit line and further connected to a local sense activation circuit through, e.g., an inverter. The turnback is done in a distance half an actual word line (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-56682).
The dummy word line reflects the actual word line length up to the farthest point. Hence, the dummy bit line reproduces the farthest bit line. The replica circuit determines the sense start timing, and generates a sense start signal (sense activation signal) and notifies the sense amplifier of the cell array of the start of sensing.
As described above, the conventional SRAM generator traces the word line WL delay and bit line BL delay corresponding to the number of rows/columns of the cell array, thereby generating a sense timing corresponding to different row/column configurations. Conventionally, since the word lines are made of polysilicon and the necessary memory capacity is small, the wiring delay up to the sense amplifier is so small as to be insignificant as compared to the dummy word line delay or dummy bit line delay. However, with the advance of process, the required memory capacity increases, and the material of word lines changes from polysilicon to a metal. Thus, although the dummy word line delay decreases, the wiring delay up to the sense amplifier becomes equal to or more than the word line delay and cannot be neglected any more. Additionally, the larger the memory capacity becomes, the larger the difference between the word line delay and the wiring delay up to the sense amplifier becomes. It is therefore difficult to ensure an optimum sense margin for each of the SRAMs having different memory capacities and configurations. That is, it is difficult to form a generator.